The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
An integrated circuit (IC) package includes an IC. The IC may include analog and/or digital circuits. Analog circuits may include, but are not limited to, operational amplifiers, sensors, and analog-to-digital converters. Digital circuits may include, but are not limited to, combinational logic, microprocessors, memory, and external interface circuits. The IC may include a system-on-chip (SoC) that includes multiple analog/digital circuits. For example, the SoC may include microprocessors, memory, analog-to-digital converters, and operational amplifiers.
The IC may be attached to a substrate. Throughout the disclosure, the term “attach” refers to a bonding of two surfaces with a bonding material. For example, a die attach paste may attach a surface of the IC to a surface of the substrate. The IC may be connected to IC package leads and may be encapsulated. The IC package leads typically connect the IC to a printed circuit board (PCB). The PCB may include other IC packages and/or discrete components that may communicate with the IC.
Referring now to FIG. 1A, an IC package 100 includes a package substrate 102, an IC 104, and an encapsulant 106. The package substrate 102 includes a PCB bonding surface 108, an IC bonding surface 110, and substrate interconnects 112. The PCB bonding surface 108 includes PCB bond pads 114-1, 114-2, . . . , and 114-n (collectively PCB bond pads 114). The IC 104 may connect to the PCB or another IC (both not shown) through the PCB bond pads 114.
The PCB bond pads 114 may be connected to the PCB using solder balls 116-1, 116-2, . . . , and 116-n (collectively solder balls 116). The PCB bond pads 114 and the solder balls 116 may include any bonding structure suitable for connecting the IC package 100 to the PCB or to another IC package. For example only, the PCB bond pads 114 and the solder balls 116 may include a ball grid array (BGA) with solder balls 116. The PCB bond pads 114 and the solder balls 116 may also include a land grid array (LGA) without solder balls 116.
The IC bonding surface 110 includes substrate bond pads 118-1, 118-2, . . . , and 118-n (collectively substrate bond pads 118). The substrate bond pads 118 are connected to the PCB bond pads 114 through the substrate interconnects 112. The substrate interconnects 112 include conductive traces and conductive vias that are integral to the package substrate 102. The package substrate 102 may include a single layer of conductive traces or multiple layers of conductive traces. For example only, the conductive traces may be located on the PCB bonding surface 108 and the IC bonding surface 110. The conductive vias may connect the conductive traces of the PCB bonding surface 108 and the conductive traces of the IC bonding surface 110.
The IC 104 includes an IC top surface 120 and an IC bottom surface 122. The IC bottom surface 122 is attached to the IC bonding surface 110 of the package substrate 102. The IC 104 may be attached to the package substrate 102 using any suitable adhesive. For example only, the adhesive may include a die attach paste or a die bonding film. The IC top surface 120 includes IC bond pads 124-1, 124-2, . . . , and 124-n (collectively IC bond pads 124). The IC bond pads 124 are connected to the substrate bond pads 118 using bonding wires 126-1, 126-2, . . . , and 126-n (collectively bonding wires 126). The IC 104 is covered with the encapsulant 106. The encapsulant 106 protects the IC 104 from physical damage and corrosion. The encapsulant 106 may be ceramic or polymer based.
The IC bond pads 124 may be connected to the PCB bond pads 114 in numerous ways. A single IC bond pad 124 may be connected to a single PCB bond pad 114. A single IC bond pad 124 may be connected to a plurality of the PCB bond pads 114. A plurality of the IC bond pads 124 may be connected to a single PCB bond pad 114.
Throughout the disclosure the term “top surface” refers to a surface of an IC that includes IC bond pads 124. Throughout the disclosure the term “bottom surface” refers to a surface of the IC that may not include IC bond pads 124. For example, as shown in FIG. 1A, the IC top surface 120 includes IC bond pads 124 and the IC bottom surface 122 does not include IC bond pads 124.
Referring now to FIG. 1B, a stacked IC package 150 includes the package substrate 102, a top IC 152, a bottom IC 154, and a spacer 156. The IC bottom surface of the bottom IC 154 is attached to the IC bonding surface 110 of the package substrate 102. The spacer 156 is attached to the IC top surface of the bottom IC 154 and the IC bottom surface of the top IC 152. The spacer 156 provides structural support for the top IC 152. The spacer 156 may also provide clearance for the bonding wires 126 that connect the bottom IC 154 to the substrate bond pads 118. The spacer 156 may include an insulating material such as oxidized silicon.
The IC bond pads 124 of the top IC 152, the IC bond pads 124 of the bottom IC 154, and the PCB bond pads 114 of the package substrate 102 may be connected in numerous ways. The IC bond pads 124 of the top IC 152 may be connected to the IC bond pads 124 of the bottom IC 154 through the substrate interconnects 112. The IC bond pads 124 of the top IC 152 may be connected to the PCB bond pads 114 through the substrate interconnects 112. The IC bond pads 124 of the bottom IC 154 may be connected to the PCB bond pads 114 through the substrate interconnects 112.
Referring now to FIG. 2A, a window IC package 200 includes a package substrate 204 having a window 208. The package substrate 204 is hereinafter called a window package substrate 204. The window 208 is hereinafter called a substrate window 208. The window IC package 200 further includes an IC 202 that is attached to the window package substrate 204. The IC 202 is hereinafter called a window IC 202. The encapsulant 106 encapsulates the window package substrate 204 and the window IC 202.
The window package substrate 204 includes a window PCB bonding surface 206 and a package IC bonding surface 210. The window PCB bonding surface 206 may include the PCB bond pads 114 and window bond pads 212. The substrate window 208 is an opening defined by the window package substrate 204. The substrate window 208 extends from the window PCB bonding surface 206 to the package IC bonding surface 210. The substrate window 208 allows for connection of the window bond pads 212 to the window IC 202 using bonding wires 126.
The window IC 202 includes a window IC top surface 214 and a window IC bottom surface 216. The window IC top surface 214 is attached to the package IC bonding surface 210. The window IC top surface 214 includes window IC bond pads 218. The window IC bond pads 218 are accessible through the substrate window 208. The window IC bond pads 218 may be connected to the window bond pads 212 using bonding wires 126 that pass through the substrate window 208. The window bond pads 212 may be connected to the PCB bond pads 114 through the substrate interconnects 112. The window bond pads 212, the window IC bond pads 218, and the substrate window 208 may be covered by the encapsulant 106. For example only, the encapsulant 106 may include an epoxy.
Throughout the disclosure, the term “window IC top surface” refers to a surface of the window IC 202 that includes window IC bond pads 218. Throughout the disclosure, the term “window IC bottom surface” refers to a surface of the window IC 202 that may not include window IC bond pads 218. For example, as shown in FIG. 2A, the window IC top surface 214 includes the window IC bond pads 218 and the window IC bottom surface 216 does not include the window IC bond pads 218.
Referring now to FIG. 2B, the window bond pads 212 are located at a perimeter 220 of the substrate window 208. The window bond pads 212 are connected to the window IC bond pads 218 using bonding wires 126. The window bond pads 212 are connected to the PCB bond pads 114 and solder balls 116 on two sides of the perimeter 220 through the substrate interconnects 112.
Referring now to FIG. 3, ICs may be stacked in a package-on-package (PoP) configuration. A PoP stack 300 includes a top IC package 302 and a bottom IC package 304. The bottom IC package 304 includes the package substrate 102, the IC 104, the spacer 156, and a PoP substrate 306. The IC bottom surface of the IC 104 is attached to the IC bonding surface 110 of the package substrate 102. The spacer 156 is attached to the IC top surface of the IC 104. The PoP substrate 306 is attached to the spacer 156.
The PoP substrate 306 includes PoP substrate bond pads 310 and the substrate interconnects 112. The solder balls 116 may connect the PCB bond pads 114 of the top IC package 302 to the PoP substrate bond pads 310. The bonding wires 126 may connect the PoP substrate bond pads 310 to the substrate bond pads 118. An IC of the top IC package 302 may connect to the IC 104 and the PCB bond pads 114 of the package substrate 102 through the substrate interconnects 112 of the package substrate 102. The IC 104 may connect to the PCB bond pads 114 of the package substrate 102 through the substrate interconnects 112 of the package substrate 102.